1. Technical Field
Various embodiments of the present invention relate to a semiconductor integrated circuits and related methods. In particular, certain embodiments relate to a semiconductor integrated circuit and a control method thereof.
2. Related Art
A semiconductor integrated circuit often uses a multi-chip package including two or more chips in order to improve the degree of integration of the semiconductor integrated circuit.
As illustrated in FIG. 1, a typical semiconductor integrated circuit 1 has a stacked structure of a master chip (hereinafter, referred to as a master) and a slave chip (hereinafter, referred to as a slave) by way of one or more through-silicon vias (TSVs).
The master includes a peripheral area, a TSV area A for signal transfer, and a TSV area B for physical support and supply of power. The master has no memory area.
The slave includes a peripheral area, a TSV area A′ for signal transfer, a TSV area B′ for physical support and supply of power, and memory areas. The memory areas of the slave may, for example, use dynamic random access memories (DRAMs) and may be divided into eight memory banks BK0 to BK7.
Each memory bank of the slave includes redundant cells for a repair operation which substitute for failed normal cells.
Furthermore, a fuse set, a control logic circuit and others related to the repair operation, are positioned between the memory banks, between the memory bank and the peripheral area, between the memory bank and the TSV area, and the like.
As illustrated in FIG. 2, the master includes a circuit for generating a row active signal RACT, wherein the circuit may include a plurality of NAND gates ND1 and ND2, a plurality of transistors M1 and M2, and a plurality of inverters IV1 to IV4.
Row active signals RACT must be provided corresponding to the number of the memory banks. Therefore, a number of the circuits illustrated in FIG. 2 are provided corresponding to the number of the memory banks.
The circuit illustrated in FIG. 2 generates the row active signal RACT in response to an active pulse ACTP, a slice address signal SLICE, a row active signal RACT, and a precharge pulse PREP.
As illustrated in FIG. 3, the slave includes a word line driving circuit 10 for driving word lines, wherein the word line driving circuit 10 includes a plurality of fuse blocks 11, a determination unit 13, a driver block (RMWL DRV) 14, a driver block (BAX DRV) 16, a driver block (FX DRV) 18, a mat selection unit 15, and a decoder 17.
The fuse blocks 11 compare a row address signal RA with repair address signals to generate signals HITB<0:N>.
The repair address signals are stored by selectively cutting fuses of the fuse blocks.
The determination unit 13 combines the row active signal RACT with the signals HITB<0:N> to generate various signals XHITB<0:M>, NXEB, and RAX2<0:1>.
The signals XHITB<0:M> are used to define the activation of redundant main word lines RMWL<0:M>. The signal NXEB is used to prevent the activation of the repair address signals, that is, normal word lines defined by fuse data. The signals RAX2<0:1> are address signals for designating sub-word lines, and correspond to an example in which main word lines and sub-word lines have been coded at the rate of 1:4.
The mat selection unit 15 generates an enable signal EN for preventing the activation of the normal word line in response to the signals XHITB<0:M> and NXEB, and selecting a sub-word line corresponding to a redundant cell array of a cell mat 20.
The decoder 17 decodes the row address signal RA and generates an address signal LAX.
The driver block 14 drives the redundant main word lines RMWL<0:M> corresponding to the signals XHITB<0:M>.
The driver block 16 drives the address signals RAX2<0:1> to generate an address signal BAX.
The driver block 18 drives the address signal BAX to generate a sub-word line driving signal FX.
As illustrated in FIG. 4, the determination unit 13 includes logic circuits 13-1 to 13-3.
The logic circuit 13-1 combines the output signals HITB<0:N> of the fuse blocks 11 with the row active signal RACT to generate the signals XHITB<0:M>.
FIG. 4 illustrates only a configuration in which the logic circuit 13-1 generates the signal XHITB<0>, and (M+1) logic circuits 13-1 are provided in order to generate the signals XHITB<0:M>.
The logic circuit 13-2 combines signals having even sequences with signals having odd sequences among the output signals HITB<0:N> of the fuse blocks 11 to generate signals HITSUM_EVEN and HITSUM_ODD.
The logic circuit 13-3 combines the signals HITSUM_EVEN, HITSUM_ODD, and RACT to generate the address signals RAX2<0:1> and the signal NXEB.
Since the slave includes the memory area but the master includes no memory area in the typical semiconductor integrated circuit 1, chip sizes of the master and the slave are different from each other.
Therefore, in order to simply connect the master to the slave with each other through the TSV, it is necessary to increase the chip size of the master.
As described above, in a typical semiconductor integrated circuit, the inefficient increase in the chip size of the master results in a reduction in a net die.
Furthermore, a slave of a typical semiconductor integrated circuit has normal cells and redundant cells, and performs a repair operation by itself, that is, an association operation for determining whether to repair a memory cell to be accessed.
Therefore, since an additional time is required to perform an operation for comparing fuse data with an external address signal for the repair operation, asynchronous parameters may increase.